Altera Integrates FPGA Timing Closure With Release of Quartus II Version 2.1 Design Software

New Version of Software Significantly Accelerates Timing Closure For High-Density Digital Logic Design

SAN JOSE, Calif., July 15 /PRNewswire-FirstCall/ -- Altera Corporation (Nasdaq: ALTR - News) today released version 2.1 of the Quartus® II design software, featuring a new timing closure methodology based on ASIC design techniques that can significantly accelerate the process of meeting timing requirements in multi-million gate system-on-a-programmable-chip (SOPC) designs. Altera is the first programmable logic supplier to deliver a methodology for timing closure as an integrated part of its existing tool suite.

As designers integrate multiple high-speed clock domains and complex intellectual property (IP) cores into large multi-million gate designs, they require new analysis and assignment tools to simplify the process of meeting their design's timing requirements. The Quartus II version 2.1 tool builds upon the LogicLock(TM) block-based design flow, introduced a year ago to increase designers' control over place-and-route, by offering improved integration between analysis and assignment tools. The emphasis on timing closure strengthens the Quartus II design software's support for Altera's new Stratix(TM) device family, which can support up to 40 unique clocks in a single device.

"Altera is taking a common sense approach to delivering the development tools required to support today's high-density FPGAs," said Rich Wawrzyniak, senior analyst, ASIC/SoC at Semico Research. "For a reasonable price, the Quartus II 2.1 design software delivers a compelling set of features allowing designers to quickly achieve timing closure in their most complex, multi- million gate designs."

Push-Button Netlist Optimizations

The new release of the software includes performance enhancing netlist optimizations in a push-button fashion. These new netlist optimization features can result in an up to 10-15 percent performance improvement over designs that do not use these optimizations. The Quartus II version 2.1 development software also includes improvements to the integrated synthesis tool. This new synthesis technology also includes language extractors licensed from Verific Design Automation Inc.

Timing Closure Interactive Floorplan

"In addition to Altera providing the best push-button FPGA performance available today, we are also giving designers control over the management of timing on complex SOPC designs," said Tim Southgate, vice president of software and tools marketing at Altera. "The Quartus II version 2.1 tool is the industry's best tool for extracting optimum performance from large FPGA designs with multiple high-speed clock domains."

Altera is also introducing the timing closure interactive floorplan, a powerful analysis tool that saves designers time and effort when interpreting the timing on the device. One of the most advanced innovations in the Quartus II version 2.1 software, the timing closure interactive floorplan provides designers with nine views of timing and placement within the device. Designers can view hierarchical timing relationships between various blocks in a design and edit, or create, timing and placement constraints within the design to optimize performance.

Path-Based Assignments

The Quartus II version 2.1 design software includes a new user-controlled optimization technique that can further reduce iterations in the place-and- route stage of the design flow. By using path-based assignments, the design engineer can easily make timing assignments to all points along a critical path identified by the timing analysis. Design engineers can reassign failing paths to a new LogicLock region and then recompile without having to go back and restructure their HDL code.

SOPC Builder Integration

An additional enhancement to the Quartus II design software is the inclusion of the SOPC Builder tool for system-level development. SOPC Builder is an automated system development tool that dramatically simplifies the task of creating high-performance SOPC designs. The tool automates the system definition and integration phases of SOPC development. Using SOPC Builder, designers can define a complete system, from hardware to software, within one tool and in a fraction of the time of traditional SOC design.

Spotlight on Verification

With the Quartus II version 2.1 tool, Altera will be extending this leadership to add support for formal verification and design rule checking tools. In concert with existing simulation tools, Altera designers can now use Conformal LEC from Verplex to verify the functional correctness of their designs. With support for design rule checkers such as Atrenta's Spyglass and Synopsys' LEDA, Altera designers can check for bugs in their designs before synthesis and simulation.

Pricing and Availability

Quartus II version 2.1 design software is now shipping to all customers on active software subscription. Altera's software subscription program simplifies the process of obtaining Altera design software by consolidating all software products and maintenance charges into one annual subscription payment. The annual subscription for the Altera design software is $2,000 for a node-locked PC license, which includes full-featured Quartus II and MAX+PLUS® II design software, OEM synthesis tools from Exemplar Logic, OEM simulation tools from Model Technology, and 12 months of software upgrades. New or existing customers may obtain a software subscription on-line on the Altera web site, http://www.altera.com , or from Altera distributors worldwide. The Quartus II software supports major operating systems, including Windows XP, Windows 2000, Windows NT, Windows 98, Sun Solaris, and HP-UX and Red Hat Linux version 7.1.

About Altera

Altera Corporation is the world's pioneer in system-on-a-programmable-chip (SOPC) solutions. Combining programmable logic technology with software tools, intellectual property, and technical services, Altera provides high-value programmable solutions to approximately 14,000 customers worldwide. More information is available at http://www.altera.com .

NOTE: Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all other words that are identified as trademarks and/or service marks are, unless noted otherwise, the trademarks and service marks of Altera Corporation in the U.S. and other countries. All other product or service names are the property of their respective holder.

CONTACT: Bruce Fienberg of Altera Corporation, +1-408-544-6397, or newsroom@altera.com.